1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a multi-level memory cell that can store several bits of digital data. Thus, the bit storage capacity per unit chip area is enhanced and complicated peripheral circuits are not needed.
2. Description of the Prior Art
With CMOS technology deepening to below sub-micron, the density of flash memory has been enhanced and thus the cost per bit can be cut down. Several kinds of memories with multi-level structures have been developed, such as DRAM, SDRAM, and flash memory. Multi-level flash memory is presently the most popular.
Conventionally, one flash memory cell could store only one bit of digital data (binary 0 or 1). In the reading operation, two levels of threshold voltage are provided according to the charge amount stored in the floating gate of flash memory cell. When charges are injected into the floating gate, representing xe2x80x9cbinary 0xe2x80x9d, the threshold voltage is higher. If no charge is present in the floating gate, representing xe2x80x9cbinary 1xe2x80x9d, the threshold voltage is lower. Therefore, a two-level flash memory cell is used to store one bit. If one memory cell has more than two levels of threshold voltage, such as four levels, eight levels or more, that is, multi-level memory cell, it is possible to store two bits, three bits or more, respectively. Thus, the storage capacity per unit chip area is enhanced.
Several kinds of multi-level flash memory cell structures, such as common ground, DINOR, AND, NOR, NAND, have been researched. In the writing operation, CHE (Channel Hot Electron) injection mode or FN (Fower-Nordheim) tunnel mode is used to write in the above-mentioned multi-level flash memory cell structures. In order to control the charge amount injecting into the floating gate, several levels of voltage are provided on the control gate and source/drain junctions. In the earsing operation, FN tunnel mode is generally used.
Multi-storage flash memory is another memory structure capable of storing several bits of digital data. In the multi-storage flash memory charge is stored in different floating gates. The writing, reading and erasing conditions are the same as in a single bit flash memory, e.g., each flash memory cell storing one bit of digital data, but their structures are different. Y. Ma et al. disclose a dual-bit split-gate (DSG) flash memory cell in xe2x80x9cA dual-bit split-gate (DSG) EEPROM cell in contactless array for single-Vcc high density flash memoriesxe2x80x9d, IEDM Tech. Dig., 1994, pp. 57-60. FIG. 1 shows one DSG flash memory cell comprising two doped regions 12 and 14 serving as source/drain in the substrate 11, two floating gates 15 and 16, a selected gate 17, a control gate 18 and a transfer gate 19. The DSG flash memory cell comprises two memory units with one pair common source/drain 12 and 14 to store two bits.
For conventional multi-level flash memory, different voltages levels are needed to perform a writing operation; thus, peripheral circuits are more complicated.
Furthermore, reliability is worse then the single bit flash memory. On the other hand, the performance and reliability of the multi-storage flash memory are similar to the single bit memory, but the memory cell occupies much more area and peripheral circuits are also complicated.
The present invention provides a multi-level memory cell combining the advantages of multi-level and multi-storage memories. The multi-level memory cell of the present invention does not require complicated peripheral circuits and its reliability is the same as that of conventional memories. Its size falls between that of the conventional multi-level memory and multi-storage memory.
In first embodiment of the present invention, a multi-level memory cell comprises a substrate, a first floating gate, a second floating gate, and a control gate. A first doped region, a second doped region, and a channel region located between the first doped region and the second doped region are provided in the substrate, wherein the first and second doped regions have different dosages and implant energies. The first floating gate is located over the channel region and near the first doped region. The second floating gate is located over the channel region and near the second doped region and isolated from the first floating gate. The control gate is located over the first floating gate and the second floating gate.
In a second embodiment of the present invention, a multi-level memory cell comprises a substrate, a first floating gate, a second floating gate, a control gate, and an erasing gate. A first doped region, a second doped region, and a channel region located between the first doped region and the second doped region are provided in the substrate, wherein the first and second doped regions have different dosages. The first floating gate is located over the channel region and near the first doped region. The second floating gate is located over the channel region and near the second doped region and isolated from the first floating gate. The control gate is located over the first floating gate and the second floating gate. The erasing gate is located beside the first and the second floating gates.
In the present invention, the first doped region and the second doped region serve as source and drain. Because the concentrations and junction depths of source and drain are different, different charges can be stored in the first floating gate and the second floating gate using the same bias voltage. Thus, a multi-level memory is obtained without complicated peripheral circuits.